SDI's proprietary time resolved measurement technique creates a precise, leakage corrected C-V plot in 1-2 minutes. Smart software automatically extracts the dielectric charge and interface parameters, and the approach has been demonstrated on advanced, ultra thin dielectrics as low as 6Å. The corona based technique provides capabilities exceeding those of traditional MOS measurements: EOT extraction is performed using a unique simulation method which provides accurate data over a wide variety of dielectrics and interface properties. The patented Q-Q method for interface state density analysis provides a quazistatic distribution of traps with the silicon band gap.

The latest generation of FAaST tools provide:
- fully automated, non-contact C-V measurements for a wide range of advanced dielectrics
- automatic extraction of dielectric capacitance, EOT, flatband voltage, interface trap density, and total oxide charge.
- Application specific modes – such as trapped charge measurements in programmed and erased states of charge trap flash memory structures.
- Contour mapping showing cross wafer variations.
- Fully automated operation, with multiple security levels designed for the manufacturing environment.
- Options such as SMIF / FOUP loadports, automatic lot ID, wafer OCR, and fully SEMI compliant automation for data upload and remote system control.
- Automatic internal calibration of voltage, and corona charge deposition.

The FAaST 200 series can be configured for multiple wafer sizes from 100mm-200mm, and FAaST 300 series for 200mm-300mm wafers. SDI C-V is also available in stand alone manual wafer load systems.

Leakage corrected C-V plot for ~11Å SiO2
C-V results
C-V results